This invention relates generally to frequency multipliers, and more particularly, to a frequency multiplier having a common-mode feedback.
Frequency multipliers are commonly used in radio applications (e.g., radio transmitter or receiver) and other radio frequency (RF) applications, such as radar applications (e.g., automotive radar) to multiply the base frequency of an oscillator by a predetermined factor (e.g., factor of 2 or 3). The multiplied frequency is driven in a final stage to produce a signal output, for example, to an antenna. Frequency multipliers allow the use of a stable frequency reference source (e.g., a crystal oscillator or on-chip voltage controlled oscillator (VCO)), to generate frequencies which may be difficult to produce directly from the VCO (e.g., 24 GHz operation). In digital applications, frequency multipliers are often used in phase-locked loops to generate a desired frequency from an external reference frequency.
Known frequency multipliers, for example, frequency triplers that triple the input frequency, typically operate by driving one or more transistors to a nonlinear region of operation. In this nonlinear region of operation, higher order harmonics are generated. A bandpass filter is then used to output the desired harmonic frequency based on the desired frequency factor multiple. For example, in a frequency tripler, the bandpass filter outputs third harmonics while suppressing the other frequency components (i.e., harmonics). However, these known frequency multipliers require a substantial input power in order to drive the transistor hard enough to generate the desired harmonics. Additionally, the efficiency of generating the harmonics in these known frequency multipliers is typically low and becomes worse as the frequency increases, thereby also degrading system performance.